1. Field of the Invention
The present invention relates to a layout structure in semiconductor devices. More particularly, the present invention relates to a word line strap layout structure used in memory devices.
2. Description of the Related Art
In a high-capacity memory device, the memory array is usually divided into many memory areas that are separated by field oxide (FOX) layers, wherein each memory area may store 8 Mbits, 32 Mbits or 64 Mbits of data. The polysilicon or polycide (polysilicon silicide) word lines of the memory array cross over different memory areas and the field oxide layers between them. To lower the resistance of the word lines, the word lines between the memory areas (or on the field oxide layers) are electrically connected to upper metal lines via contacts to form word line strap structures. Since the resistance of a metallic material is much lower than that of polysilicon or polycide, the RC delay effect of the memory device is substantially reduced with such a design.
FIG. 1A illustrates a top view of a conventional word line strap layout structure, and FIG. 1B illustrates a cross-sectional view of the same along line I-I″. FIG. 2 illustrates a drawback of adopting the conventional word line strap layout in a memory device.
Referring to FIGS. 1A-1B, a polysilicon word line 104 crosses over a field oxide layer 102 on a substrate 100 between two memory areas 10, and is electrically connected to a metal line 108 via a contact 106 over the field oxide layer 102 to form a word line strap structure. The field oxide layer 102 usually has a thickness up to 5000-6000Ã□ in consideration of high operating voltages, so a large step height is created between the field oxide layer 102 and the adjacent memory areas 10.
Referring to FIG. 2, since both the height and the width of the field oxide layer 102 are large, the critical dimensions of the photoresist patterns 110 for defining bit lines (not shown) near the edges of the memory areas 10 are affected by the field oxide layer 102. Therefore, the critical dimensions of the bit lines near the edges of the memory areas 10 are not within an acceptable range, and the bit lines have to be taken as dummy bit lines. Consequently, the integration of the memory array is reduced.